In software development, make is a utility for automatically building large applications. Files specifying instructions for make are called Makefiles. make is an expert system that tracks which files have changed since the last time the project was built and invokes the compiler on only those source code files and their dependencies. Before make's introduction, the Unix build system would most likely consist of "make" and "install" shell scripts accompanying a program's source. Being able to combine the commands for the different targets into a single file, and being able to abstract out dependency tracking and archive handling, was an important step in the direction of modern build environments. BSD make, which is derived from Adam de Boor's work on a version of make capable of building targets in parallel, and survives with varying degrees of modification in FreeBSD, NetBSD and OpenBSD. Most notably, it has conditionals and iterative loops which are applied at the parsing stage and may be used to conditionally, and programmatically, construct the makefile, including generation of targets at runtime. GNU make, which is part of most Linux installations and is frequently used in conjunction with the GNU build system. Its departures from traditional make are most noticeable in pattern-matching in dependency graphs and build targets, as well as a number of functions which may be invoked to have the make utility do things like collect a list of all files in the current directory. POSIX includes standardization of the basic features and operation of the make utility, and is implemented with varying degrees of completeness in Unix-based versions of make. In general, simple makefiles may be used between various versions of make with reasonable success. Some versions of GNU make and BSD make will look first for files named "GNUmakefile" and "BSDmakefile" respectively, which allows one to put makefiles which use implementation-defined behaviour in separate locations. In its basic form, Make requires the programmer to manually track all dependencies between files in the project. This process is error prone, since a forgotten or an extra dependency might not be immediately obvious, but instead surfaces as subtle bugs in the software. It is possible to create make files that generate some of these dependencies, but a more common solution is to use one of the available generators to make, e.g. Automake toolchain provided from the GNU Project. Another problem not well handled by make is the tailoring of a build process to a given platform. E.g, the compiler used on one platform might not accept the same options as the one used on another. This problem is typically handled by generating platform specific build instructions, which in turn are processed by make. Common tools for this process are Autoconf and Cmake. The syntax used by Make includes the use of tab, a whitespace character. Many editors do not provide very clear visual clues to the presence of tabs rather than spaces, and tab characters are not represented uniformly across editors in any case, with size varying from as little as 2 spaces to 8 spaces. Thus, the syntax of make is often subject to criticism. Some projects, such as Apache Ant, have attempted to redo make with a better syntax, with mixed success. For programmers using makefile generators, this issue is likely unimportant. With the advent of modern Integrated Development Environments, especially on non-Unix platforms, many programmers do not manually manage dependency tracking, or even the listing of which files are part of a project. Instead, the task is automated by the integrated environment. Likewise, many modern programming languages have language-specific ways of listing dependencies which are more efficiently tracked through the use of language-specific build utilities. These approaches typically have the drawback that support for arbitrary build instructions is limited. A makefile consists of lines of text which define a file (or set of files) or a rule name as depending on a set of files. Output files are marked as depending on their source files, for example, and source files are marked as depending on files which they include internally. After each dependency is listed, a series of lines of tab-indented text may follow which define how to transform the input into the output, if the former has been modified more recently than the latter. In the case where such definitions are present, they are referred to as "build scripts" and are passed to the shell to generate the target file. The basic structure is:[1] A makefile also can contain definitions of variables and inclusion of other makefiles. Variables in makefiles may be overridden in the command line arguments passed to the make utility. This allows users to specify different behaviour for the build scripts and how to invoke programs, among other things. For example, the variable "CC" is frequently used in makefiles to refer to a C compiler, and the user may wish to provide an alternate compiler to use.
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